The present invention relates to circuitry for adding a binary number A to a binary number B and/or for summing binary number A, the binary number B and the number 1, and, more particularly, the invention relates to circuitry that simultaneously provides the sum of the binary numbers A and B and the sum of the binary numbers A, B and 1. Other embodiments of the invention include circuitry for selectively summing the binary numbers A and B or the binary numbers A, B, and 1.
FIG. 1 illustrates known circuitry for summing the binary number A and the binary number B. The binary number A is represented as a series of bits ai where i is the binary weight of the bit ai and increases from the value zero for the least significant bit of A in steps of one to the value of the most significant bit of A. In the examples, A and B are eight bit numbers although only three bits are shown in FIG. 1. The binary number B is a series of bits bi where i is the binary weight of the bit. The summation of the numbers A and B is represented by the binary number S which is a series of bits si where i is the binary weight of the bit. The summation of the numbers A, B, and 1 is the number Sxe2x80x2 which is a series of bits sxe2x80x2i, where i is the binary weight of the bit. The addition circuitry illustrated in FIG. 1 receives as inputs the number A, the number B, and an initial carry-in value c0. The circuitry produces the number S if the initial carry-in value c0 is zero and the number Sxe2x80x2 if the initial carry-in value c0 is one. The addition circuitry has a sequence of full adders. The first full adder receives the least significant bit of the numbers A and B and the initial carry-in value c0. It produces the least significant bit of the summation signal S or Sxe2x80x2 and a first carry-in value c1. The second full adder has the binary weight of one, and receives the first carry signal c1 and the bit values a1 and b1. The second full adder produces as an output S1 or Sxe2x80x21 and the second carry value c2. There will generally be as many full adders serially interconnected as there are bits in the numbers A and B.
The relationship of the bits si output from the full adders when the initial carry-in c0 is zero to the bits ai and bi received is illustrated in equation 1. In this equation i represents the binary weight, ai is the ith bit of A, bi is the ith bit of B, gi is the bit generate, pi is the bit propagate, ci is the carry produced by the ith full adder and si is the ith bit of S, the sum of A and B.
Equation 2 illustrates the relationship of the output of the ith full adder to the bit values ai and bi when the initial carry value c0 is one. The symbol i represents the binary weight of a bit. ai is the ith bit of A, bi is the ith bit of B, gi is the bit generate, pi is the bit propagate, ci is the carry produced by the ith full adder and Sxe2x80x2i is the ith bit of the number Sxe2x80x2 which is the sum of A, B and 1.
Addition circuitry is commonly used to round a fractional number up or down to the nearest full number. By controlling the value of the initial carry-in value c0 the output from the circuitry can represent either the rounded up sum Sxe2x80x2, i.e. A+B+1 or the rounded down sum A, i.e., A+B.
Addition circuitry is also commonly used to find the difference between two binary numbers A and B where A and B are expressed as two""s complement. When a number is expressed in two""s complement format, it can be negated by either inverting all the bits of the number and then adding one or by subtracting one and then inverting all the bits of that number. Consequently, by performing appropriate inversions, addition circuitry can be used to create an output signal which represents a difference of two numbers.
In current video encoding standards, it is often necessary to find the absolute difference (i.e., unsigned (+ve) difference) between two numbers. According to the MPEG video encoding standards, the video is encoded by comparing how a picture changes frame by frame rather than reproducing the whole picture frame by frame. It is consequently necessary to determine whether a picture has changed from one frame to the next. This may be achieved by comparing a block of pixels in a frame to a number of blocks in the next frame to establish the block with the smallest difference. A number can be used to represent the attributes of a pixel. As attributes of the pixel change so does the number. Consequently, by comparing such numbers for one frame with the equivalent numbers for the next frame it can be deduced how the picture has changed from one frame to the next. It is therefore important in video encoding to be able to find the difference between two numbers. Normally, two separate circuits will be provided, one circuit that calculates the value of the first number minus the second number and another circuit that calculates the value of the second number minus the first number.
FIG. 2 illustrates in more detail addition circuitry 30 for summing A and B to produce S. The bit a0 and the bit b0 are supplied as inputs to an AND gate 20 which produces the bit generate g0. The bit a0 and the bit b0 are also supplied as inputs to an XOR gate 40 which produces s0 as its output. The bit a1 and the bit b1 are supplied as inputs to an XOR gate 41 which produces the first bit propagate signal p1. The bit generate signal g0 and the first bit propagate signal p1 are supplied as inputs to an XOR gate 241 which produces the bit s1. The bit a1 and the bit b1 are also supplied as inputs to an OR gate 61 which supplies its output as a first input to an AND gate 81. The second input of the AND gate 81 is received from the output of the AND gate 20. The output of the AND gate 81 provides a first input to an OR gate 101. The second input to the OR gate 101 is received from an AND gate 21 which receives as inputs the bit a1 and the bit b1. The bit a2 and the bit b2 are supplied as inputs to an XOR gate 42 which provides its output as a first input to a XOR gate 242. The second input to the XOR gate 242 is provided by the output of the OR gate 101. The output of the XOR gate 242 provides the bit S2. The bit a2 and the bit b2 are also combined in an OR gate 62 to produce a first input to an AND gate 82 which receives as a second input the output from the OR gate 101. The output from the AND gate 82 supplied as a first input to a OR gate 102. The second input to the OR gate 102 is supplied by a AND gate 22 which receives as an input the bits a2 and b2.
The output of the OR gate 102 is supplied as a first input to a XOR gate 243. The second input to the XOR gate 243 is supplied by the output of an XOR gate 43 which receives as inputs the bit a3 and the bit b3. The output of the XOR gate 243 provides the bit s3. An AND gate 23 also receives the bits a3 and b3 and provides its output as a first input to a OR gate 163. The second input to the OR gate 163 is provided by an AND gate 143 which receives as a first input the output from the AND gate 22 and as a second input the output from an OR gate 63 which receives as inputs the bit a3 and bit b3. The output from the OR gate 63 is also provided as a first input to an AND gate 123 which receives as a second input the output from the OR gate 62.
The output from the AND gate 123 is supplied as a first input to an AND gate 83 which receives as a second input the output from the OR gate 101. The output from the AND gate 83 and the output from the OR gate 163 are combined in an OR gate 103. A XOR gate 244 receives as a first input the output from the OR gate 103 and as a second input the output from an XOR gate 44 which receives as inputs the bit a4 and the bit b4. The XOR gate 244 produces the bit S4. An OR gate 64 receives an inputs the bit a4 and bit b4 and provides its output as a first input to an AND gate 84. The AND gate 84 receives as its second input the output from the OR gate 103 and provides its output to a OR gate 104. The other input to the OR gate 104 is provided by an AND gate 24 which receives as inputs the bit a4 and the bit b4. An XOR gate 245 produces the bit s5 and receives as a first input the output from the OR gate 104 and receives as a second input the output from an XOR gate 45 which receives as inputs the bit a5 and the bit b5. An AND gate 125 receives as a first input the output from the OR gate 64 and an output from an OR gate 65 which receives as inputs the bit a5 and the bit b5.
An OR gate 165 receives as a first input the output from an AND gate 25 which receives as inputs the bit a5 and the bit b5 and as a second input receives the output from an AND gate 145 which itself receives as inputs the output from the AND gate 24 and the output from the OR gate 65. The output from the AND gate 125 is combined with the output from the OR gate 103 in an AND gate 85 to produce a first input to a first OR gate 105. The second input to the OR gate 105 is provided by the output from the OR gate 165. The output from the OR gate 105 is provided as a first input to the XOR gate 246. The XOR gate 246 receives as a second input the output from the XOR gate 46 which receives as inputs the bit a6 and the bit b6. The XOR gate 246 produces as an output the bit S6.
An OR gate 66 receives as its inputs the bit a6 and the bit b6 and supplies its output as a first input to an AND gate 126. The second input to the AND gate 126 is supplied by the output of the AND gate 125 and the output of the AND gate 126 is supplied as a first input to an AND gate 86. The output from the OR gate 66 is supplied as a first input to an AND gate 146. The AND gate 146 receives as a second input the output from the OR gate 165 and provides an output signal to a first input of an OR gate 166. The second input to the OR gate 166 is supplied by an AND gate 26 which receives as inputs the bit a6 and the bit b6. The AND gate 86 which receives as a first input the output from the AND gate 126 receives as a second input the output from the OR gate 103 and provides its output as a first input to an OR gate 106. The second input to the OR gate 106 is provided by the output of the OR gate 166. The output of the OR gate 106 is provided as a first input to an XOR gate 247. The XOR gate 247 receives as a second input the output from an XOR gate 47 which receives as inputs the bit a7 and the bit b7. The XOR gate 247 produces the bit s7.
The bit a7 and the bit b7 are combined in an OR gate 67 to produce a first input to an AND gate 187 which receives as a second input the output from the OR gate 66. The output from the OR gate 67 is supplied as a first input to an AND gate 207. The AND gate 207 receives as a second input the output from the AND gate 26. The output from the AND gate 207 is supplied as a first input to an OR gate 227. The second input to the OR gate 227 is provided by a AND gate 27 which receives as its inputs the bit signal a7 and the bit signal b7.
An AND gate 147 receives as its inputs the output from the AND gate 187 and the output from the OR gate 165 and provides its output as a first input to an OR gate 167. The second input to the OR gate 167 is supplied by the output of the OR gate 227. The output of the OR gate 167 is provided as a first input to an OR gate 107. An AND gate 127 receives as its inputs the output from the AND gate 125 and the output from the AND gate 187. The output from the AND gate 127 is supplied as a first input to the AND gate 87. The AND gate 87 receives as a second input the output from the OR gate 103. The output from the AND gate 87 is supplied as a second input to the OR gate 107. The output of the OR gate 107 produces the last carry value c8.
FIG. 3 illustrates addition circuitry for summing the numbers A, B and c0. The value of c0 may be zero or one. When the value of c0 is zero the circuitry of FIG. 3 is functionally equivalent to that of FIG. 2 and the output value from the circuit is S. When the value of the initial carry-in value c0 is one, the circuitry produces an output signal Sxe2x80x2. The summation circuitry illustrated in FIG. 3 has addition circuitry 30 illustrated in FIG. 2 and has additional circuitry 26 enclosed by the dotted line. The additional circuitry 26 has an OR gate 60 for receiving the bit a0 and the bit bo. The OR gate 60 provides a first input to a first AND gate 80. The second input to the AND gate 80 is provided by c0. The output from the AND gate 80 is provided as a first input to an OR gate 100. The second input to the OR gate 100 is provided by the output of the AND gate 20. The output of the OR gate 100 provides one of the inputs to an XOR gate 241 and one of the inputs to the AND gate 81 and in place of the output from the AND gate 20.
It will be appreciated that the circuitry in FIG. 3 can produce as its output the value A+B or the value A+B+1 depending on the value of c0. It cannot however quickly switch between producing an output A+B and producing an output A+B+1. The value of c0 when it changes must pass through the succession of gates 8i, 10i before it can effect a change in the output signal.
It would be desirable to provide circuitry which can quickly change between producing an output value A+B and output value A+B+1 or which can simultaneously provide an output value A+B and an output value A+B+1.
According to one aspect of the invention there is provided circuitry for adding a first binary number (A) having a plurality of bits (a0, a1, . . . ) to a second binary number (B) having a plurality of bits (b0, b1, . . . ) to produce a third binary number (A+B) having a plurality of bits (s0, s1, . . . ) and/or a fourth binary number (A+B+1) having a plurality of bits (s0xe2x80x2, s1xe2x80x2 . . . ) and corresponding to the addition of the third binary number and one.
The circuitry further includes a plurality of stages wherein each stage has a first input for receiving a bit (ai) of the first binary number (A), a second input for receiving a bit (bi) of the second binary number (B) having the same binary weight (i) as the bit received at the first input and output means for producing a bit (si) of the third binary number (A+B) and/or a bit (sxe2x80x2i) of the fourth binary number (A+B+1), wherein said output means comprises Exclusive OR means for combining a first signal and a second signal to produce a bit of the third binary number and the first signal and a third signal to produce a bit of the fourth binary number wherein said third signal is equivalent to said second signal if both the bits received at the first and second inputs have a LOW logic value, or for any stage having a lower binary weight, both the bits received at the first and second inputs have a LOW logic value and is otherwise equivalent to a predetermined logic value.
Said second signal for a first stage can correspond to a high logic level if the bit of the first binary number and the bit of the second binary number received at the first and second inputs of the first stage are both high or, for a second stage having a lower binary weight, both the first and second bits received at the first and second inputs have a high logic value and in none of the stages intermediate between said first and second stage are the first and second bits input at the first and second inputs both low logic values.
Said second signal for a stage can correspond to a high logic value if the stage generates or if a preceding stage generates and one of the intermediate stages kill.
Ideally, each stage produces an output bit of the third binary number according to pmrcm and the output bit of the fourth binary number according to pmr(cm:0+km:o) where cm:0 is the group carry signal and km:0 is the group carry signal for the stage having binary weight m, and pm is the propagate bit.
According to another aspect of the invention there is provided addition circuitry for adding a first binary number (A) having a plurality of bits (a0, a1, . . . ) to a second binary number (B) having a plurality of bits (b0, b1, . . . ) to produce a third binary number (A+B) having a plurality of bits (s0, s1, . . . ) and/or a fourth binary number (A+B+1) having a plurality of bits (s0xe2x80x2, s1xe2x80x2, . . . ) and corresponding to the third binary number plus one. The circuitry includes a plurality of stages wherein each stage has a first input for receiving a bit (ai) of the first binary number (A) and a second input for receiving a bit (bi) of the second binary number (B) having the same binary weight (i) as the bit received at the first input and output means for producing a bit (si) of the third binary number (A+B) and/or a bit (si) of the fourth binary number (A+B+1). The output means includes Exclusive OR means for combining a first signal and a second signal to produce a bit of the third binary number and the first signal and a third signal to produce a bit of the fourth binary number and logic circuitry arranged to receive the second signal and a signal from the logic circuitry from the preceding stage and produce the third signal, wherein the logic circuitries of the plurality of stages emulate the application of a HIGH carry signal provided to the first stage of lowest binary weight.
The logic circuitry can include an AND gate and an OR gate. The AND gate in the preceding stage supplies a first input to the OR gate and the second input to the OR gate is the second signal.
The AND gate in each stage can produce an output with a low logic value if both the first and second bit received at that stage are low or both the first and second bit received at any preceding stage are low.
The exclusive OR means can include an XOR gate the output of which provides the bit of the third binary number or the bit of the fourth binary number in dependence on the value of a received control signal, wherein said control signal gates the first input to the OR gate of said logic circuitry.
According to a still further aspect of the invention there is provided addition circuitry for adding a first binary number (A) having a plurality of bits (a0, a1, . . . ) to a second binary number (B) having a plurality of bits (b0, b1, . . . ) to produce a third binary number (A+B) having a plurality of bits (s1, s1, . . . ) and/or a fourth binary number (A+B+1) having a plurality of bits (s0xe2x80x2, s1xe2x80x2, . . . ) and corresponding to the third binary number plus one. The circuitry includes a plurality of stages wherein each stage has a first input for receiving a bit (ai) of the first binary number (A) and a second input for receiving a bit (bi) of the second binary number (B) having the same binary weight (i) as the bit received at the first input and output means for producing a bit (si) of the third binary number (A+B) and/or a bit (si) of the fourth binary number (A+B+1). The output means includes Exclusive OR means for combining a first signal and a second signal to produce a bit of the third binary number and the first signal and a third signal to produce a bit of the fourth binary number and logic circuitry arranged to logically OR the second signal and a signal received from the logic circuitry of the preceding stage to produce the third signal and to provide a signal to the logic circuitry of the next stage dependent upon the logic value of the signal received from the preceding stage and the first and second bits received by the stage.
In one embodiment, the signal provided by the logic circuitry to the next stage has a high logic value if the signal received from the logic circuity at the preceding stage has a high logic value and one or both of the first and second bits have a high logic value.
According to a yet another aspect of the invention there is provided circuitry for adding a first binary number having a plurality of bits to a second binary number having a plurality of bits to produce a third binary number having a plurality of bits and a fourth binary number having a plurality of bits and corresponding to the third binary number plus one. The circuitry includes a plurality of stages wherein each stage includes:
a first input for receiving a bit of the first binary number;
a second input for receiving a bit of the second binary number having the same binary weight as the bit received at the first input;
first output means for producing a bit of the third binary number and comprising exclusive OR means for combining a first signal and a second signal to produce a bit of the third binary number; and
second output means for producing a bit of the fourth binary number comprising exclusive OR means for combining the first signal and a third signal to produce a bit of the fourth binary number, wherein said first and second output means produce the third and fourth binary numbers substantially simultaneously.
According to a still further aspect of the invention there is provided circuitry for adding a first binary number having a plurality of bits to a second binary number having a plurality of bits to produce a third binary number having a plurality of bits or a fourth binary number having a plurality of bits and corresponding to the third binary number plus one. The circuitry includes a plurality of stages wherein each stage includes:
a first input for receiving a bit of the first binary number;
a second input for receiving a bit of the second binary number having the same binary weight as the bit received at the first input; and
output means for producing a bit of the third binary number or a bit of the fourth binary number, wherein said output means comprises exclusive OR means for combining a first signal and a second signal to produce a bit of the third binary number or the first signal and the third signal to produce a bit of the fourth binary number, said exclusive OR means operating in dependence on the value of a single independent control signal being supplied directly to said output stage.
According to a still yet another aspect of the invention there is provided circuitry for adding a first binary number having a plurality of bits to a second binary number having a plurality of bits to produce a third binary number having a plurality of bits or a fourth binary number having a plurality of bits and corresponding to the third binary number plus one. The circuitry includes a plurality of stages wherein each stage includes:
a first input for receiving a bit of the first binary number;
a second input for receiving a bit of the second binary number having the same binary weight as the bit received at the first input; and
output means for producing a bit of the third binary number or a bit of the fourth binary number, wherein said output means comprises exclusive OR means for combining a first signal and a second signal to produce a bit of the third binary number or the first signal and a third signal to produce a bit of the fourth binary number, said exclusive OR means being supplied by logic circuitry comprising an AND gate and an inverter which are supplied in parallel with said second signal, said logic circuitry being operable to produce said second or third signal in dependence upon a control signal.
According to a further aspect of the invention there is provided circuitry for adding a first binary number having a plurality of bits to a second binary number having a plurality of bits to produce a third binary number having a plurality of bits or a fourth binary number having a plurality of bits and corresponding to the third binary number plus one. The circuitry includes a plurality of stages wherein each stage includes:
a first input for receiving a bit of the first binary number;
a second input for receiving a bit of the second binary number having the same binary weight as the bit received at the first input; and
output means for producing a bit of the third binary number or a bit of the fourth binary number, wherein said output means comprises exclusive OR means for combining a first signal and a second signal to produce a bit of the third binary number or a first signal and a third signal to produce a bit of the fourth binary number, said exclusive OR means being supplied by logic circuitry comprising an AND gate and an inverter which are supplied in parallel with said second signal, said logic circuitry being operable to produce said second or third signal in dependence upon the value of a control signal supplied from the most significant stage of carry and propagation circuitry disposed between said input and said output means.